The present invention relates to a wafer backing insert for a free mount semiconductor polishing apparatus and process wherein the wafer backing insert behind the semiconductor substrate has a diameter less than the diameter of the semiconductor substrate being polished to allow the removal rate of material at the edge of the semiconductor substrate to be less than the overall average removal rate across the substrate.
Continuous developments in very-large-scale integration (VLSI) sub-micron integrated circuit (IC) devices have led to the need for extremely flat silicon wafers to enable adequate line width resolution in microlithographic operations. The necessary wafer flatness requires total thickness variation (TTV) on the order of fractions of microns for 150 mm and larger diameter wafers during the polishing processes which produce final wafers. This ability to produce extremely flat silicon wafers has been hampered by the tendency of wafers to exhibit excessive thinning of the wafer at the edges or "edge rolloff" during polishing. This excessive thinning at the edges can lead to unwanted oxide removal on the outer portions of the wafer and a high degree of TTV.
Furthermore, semiconductor-on-insulator (SOI) wafers for many applications also require ultra low TTV's. SOI wafers produced by the bond, etch back, and polish process have an even greater tendency to exhibit an edge roll-off and thinning problem during the polishing process. The increased roll-off problem associated with SOI wafers may be due to lower thermal conductivity of the SOI wafer as compared to ordinary silicon wafers.
Historically, standard chemical mechanical polishing processes employing a conventional wafer backing insert behind the wafer have been used for final wafer polishing. The conventional wafer backing inserts generally have diameters at least equal to the diameter of the wafers being polished and generally have the same diameter as the wafer being polished. These chemical mechanical polishing processes use polishing pads in combination with polishing slurries, which are contacted with a wafer having a wafer backing insert behind it being supported by a wafer backing plate and rotatable spindle.
Conventional wafer backing inserts are generally made of a compressible material having a compressibility of between about 4% and 16%, have a thickness of between about 0.5 and 0.8 millimeters, and have a sufficient number of holes in them to allow air to be drawn from a vacuum before and after the polishing process to allow transport of the wafer between polishing tables and pads. The front side of the wafer backing insert comprises a non-woven matrix-type fabric, polymerized felt-type fabric, or other material suitable for frictionally engaging the back surface of the semiconductor wafer during polishing. The back side of the wafer backing insert comprises an adhesive type material to adhere the backing insert to the wafer backing plate during polishing. Conventional wafer backing inserts such as a DF-200 backing insert are commercially available from R. Howard Strasbaugh Inc. (San Luis Obispo, Calif.). The polishing slurry utilized throughout the polishing process is generally composed of various particle sized silica dispersed in an alkaline water base.
Although chemical mechanical polishing has generally yielded favorable results, it tends to exhibit an enhanced silicon removal rate at the edges of the wafer as the edges experience a combination of the unflexed polish pad fibers and fresh undepleted slurry. This rolloff may lead to a "dish" or "dome" shaping of the wafer, and may be further compounded by non-uniformity in pad conditioning. This wafer edge thinning problem due to deficiencies in the chemical mechanical polishing process is extremely difficult and costly to correct by reworking.